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rev 1.1.6 8/1/02 characteristics subject to change without notice. 1 of 21 www.xicor.com x9421 single digitally controlled (xdcp) potentiometer features single voltage potentiometer 64 resistor taps spi serial interface for write, read, and transfer operations of the potentiometer wiper resistance, 150 ? typical at 5v 4 non-volatile data registers non-volatile storage of multiple wiper positions power on recall. loads saved wiper position on power up. standby current < 5? max ? cc : 2.7v to 5.5v operation 2.5k ? , 10k ? end to end resistance 100 yr. data retention endurance: 100, 000 data changes per bit per register 14-lead tssop, 16-lead soic low power cmos description the x9421 integrates a single digitally controlled potentiometer (xdcp) on a monolithic cmos integrated circuit. the digital controlled potentiometer is implemented using 63 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the spi bus interface. the potentiometer has associated with it a volatile wiper counter register (wcr) and a four non- volatile data registers that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. powerup recalls the contents of the default data register (dr0) to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. block diagram 64-taps 10k ? inc / dec r h /v h r l /v l r w /v w pot v cc v ss spi bus address data status write read wiper transfer power on recall wiper counter register (wcr) data registers 4 bytes control interface bus interface & control low noise/low power/spi bus a pplication n otes available an99 ?an115 ?an120 ?an124 ?an133 ?an134 ?an135
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 2 of 21 www.xicor.com circuit level applications vary the gain of a voltage ampli?r provide programmable dc reference voltages for comparators and detectors control the volume in audio circuits trim out the offset voltage error in a voltage ampli?r circuit set the output voltage of a voltage regulator trim the resistance in wheatstone bridge circuits control the gain, characteristic frequency and q-factor in ?ter circuits set the scale factor and zero point in sensor signal conditioning circuits vary the frequency and duty cycle of timer ics vary the dc biasing of a pin diode attenuator in rf circuits provide a control variable (i, v, or r) in feedback circuits system level applications adjust the contrast in lcd displays control the power level of led transmitters in communication systems set and regulate the dc biasing point in an rf power ampli?r in wireless systems control the gain in audio and home entertainment systems provide the variable dc bias for tuners in rf wireless systems set the operating points in temperature control systems control the operating point for sensors in industrial systems trim offset and gain errors in arti?ial intelligent systems detailed functional diagram wiper counter register (wcr) r h /v h r l /v l data r w /v w interf a ce and control circuitr y v cc v ss cs sck a0 so si hold wp control 64--taps 10k ? power on recall dr0 dr1 dr2 dr3
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 3 of 21 www.xicor.com pin configuration v cc r l /v l vss 1 2 3 4 5 6 7 8 14 13 12 11 10 9 nc r w /v w sck cs tssop r h /v h x9421 s0 nc si hold wp a0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 soic x9421 v cc r l /v l r w /v w r h /v h hold wp a0 nc vss sck cs nc si so nc nc pin assignments tssop pin soic pin symbol brief description 1 2 so serial data output 2 3 nc no connect 3 nc no connect 44cs chip select 5 5 sck serial clock 6 6 si serial data input 78v ss system ground 89wp hardware write protect 9 10 a0 device address 10 11 hold device select. pause the serial bus. 11 12 r w / v w wiper terminal of the potentiometer. 12 13 r h / v h high terminal of the potentiometer. 13 14 r l / v l low terminal of the potentiometer. 14 16 v cc system supply voltage 1 nc no connect 7 nc no connect 15 nc no connect
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 4 of 21 www.xicor.com pin descriptions host interface pins serial output (so) so is a push/pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input si is the serial data input pin. all opcodes, byte addresses and data to be written to the potentiometer and pot register are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the sck input is used to clock data into and out of the x9421. chip select (cs ) when cs is high, the x9421 is deselected and the so pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. cs low enables the x9421, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. hold (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume communication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. device address (a 0 ) the address input is used to set the least signi?ant bit of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9421. a maximum of 2 devices may occupy the spi serial bus. potentiometer pins v h /r h , v l /r l the v h /r h and v l /r l inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. v w /r w the wiper output is equivalent to the wiper output of a mechanical potentiometer. hardware write protect input (wp ) the wp pin when low prevents nonvolatile writes to the data registers. writing to the wiper counter register is not restricted. system/digital supply (v cc ) v cc is the supply voltage for the system/digital section. v ss is the system ground. principles of operation the x9421 is a highly integrated microcircuit incorporating a resistor array and associated registers and counter and the serial interface logic providing direct communication between the host and the xdcp potentiometer. serial interface the x9421 supports the spi interface hardware conventions. the device is accessed via the si input with data clocked in on the rising sck. cs must be low and the hold and wp pins must be high during the entire operation. the so and si pins can be connected together, since they have three state outputs. this can help to reduce system pin count. array description the x9421 is comprised of one resistor array containing 63 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the ?ed terminals of a mechanical potentiometer (v h /r h and v l /r l inputs).
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 5 of 21 www.xicor.com at both ends of the array and between each resistor segment is a cmos switch connected to the wiper (v w /r w ) output. within the individual array only one switch may be turned on at a time. these switches are controlled by a wiper counter register (wcr). the six bits of the wcr are decoded to select, and enable, one of sixty-four switches. the block diagram of the potentiometer is shown in figure 1. wiper counter register (wcr) the x9421 contains a wiper counter register. the wcr can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wiper counter register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register instruction (parallel load); it can be modi?d one step at a time by the increment/ decrement instruction. finally, it is loaded with the contents of its data register zero (dr0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9421 is powered- down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. data registers the potentiometer has four 6-bit nonvolatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the wcr. it should be noted all operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer, the data registers can be used as regular memory locations for system parameters or user preference data. register descriptions table 1. data registers, (6-bit), nonvolatile there are four 6-bit data registers associated with the potentiometer. {d5~d0}: these bits are for general purpose nonvol- atile data storage or for storage of up to four different wiper values. table 2. wiper counter register, (6-bit), volatile {wp5~wp0}: these bits specify the wiper position of the potentiometer. 0 0 d5 d4 d3 d2 d1 d0 (msb) (lsb) 0 0 wp5 wp4 wp3 wp2 wp1 wp0 (msb) (lsb)
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 6 of 21 www.xicor.com write in process the contents of the data registers are saved to nonvolatile memory when the cs pin goes from low to high after a complete write sequence is received by the device. the progress of this internal write operation can be monitored by a write in process bit (wip). the wip bit is read with a read status command. instructions address/identification (id) byte the ?st byte sent to the x9421 from the host, following a cs going high to low, is called the address or identi?ation byte. the most signi?ant four bits of the slave address are a device type identi?r, for the x9421 this is ?ed as 0101[b] (refer to figure 2). the least signi?ant bit in the id byte selects one of two devices on the bus. the physical device address is de?ed by the state of the a 0 input pin. the x9421 compares the serial data stream with the address input state; a successful compare of the address bit is required for the x9421 to successfully continue the command sequence. the a 0 input can be actively driven by a cmos input signal or tied to v cc or v ss . the remaining three bits in the id byte must be set to 110. figure 2. address/identification byte format instruction byte the next byte sent to the x9421 contains the instruction and register pointer information. the four most signi?ant bits are the instruction. the next two bits point to one of four data registers. the format is shown below in figure 3. figure 3. instruction byte format 1 00 11 0a0 device type identifier device address 1 i1 i2 i3 i0 r1 r0 0 0 register select instructions figure 1. detailed potentiometer block diagram serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input counter register inc/dec logic up/dn clk modified sck up/dn v h v l v w 8 6 c o u n t e r d e c o d e if wcr = 00[h] then v w = v l if wcr = 3f[h] then v w = v h wiper (wcr)
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 7 of 21 www.xicor.com the four high order bits of the instruction byte specify the operation. the next two bits (r 1 and r 0 ) select one of the four registers that is to be acted upon when a register oriented instruction is issued. the last two bits are de?ed as 0. two of the eight instructions are two bytes in length and end with the transmission of the instruction byte. these instructions are: xfr data register to wiper counter register ?his instruction transfers the contents of one speci?d data register to the wiper counter register. xfr wiper counter register to data register ?his instruction transfers the contents of the wiper counter register to the speci?d associated data register. the basic sequence of the two byte instructions is illustrated in figure 4. these two-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram controlling the wiper position. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between the potentiometer and one of its associated registers. five instructions require a three-byte sequence to complete. these instructions transfer data between the host and the x9421; either between the host and one of the data registers or directly between the host and the wcr. these instructions are: read wiper counter register ?ead the current wiper position of the pot, ?r ite wiper counter register ?hange current wiper position of the pot, read data register ?ead the contents of the selected data register; ?r ite data register ?rite a new value to the selected data register. read status ?his command returns the contents of the wip bit which indicates if the internal write cycle is in progress. the sequence of these operations is shown in figure 5 and figure 6. the ?al command is increment/decrement. it is different from the other commands, because its length is indeterminate. once the command is issued, the master can clock the wiper up and/or down in one resistor segment steps; thereby, providing a ?e tuning capability to the host. for each sck clock pulse (t high ) while si is high, the selected wiper will move one resistor segment towards the v h /r h terminal. similarly, for each sck clock pulse while si is low, the selected wiper will move one resistor segment towards the v l /r l terminal. a detailed illustration of the sequence and timing for this operation are shown in figure 7 and figure 8. figure 4. two-byte instruction sequence 0101110a0 i3 i2 i1 i0 r1 r0 0 0 sck si cs
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 8 of 21 www.xicor.com figure 5. three-byte instruction sequence (write) figure 6. three-byte instruction sequence (read) figure 7. increment/decrement instruction sequence figure 8. increment/decrement timing limits 0 101 0a0 i3 i2 i1 i0 r1 r0 0 0 scl si 0 0 d5 d4 d3 d2 d1 d0 cs 11 0101 0a0 i3 i2 i1 i0 r1 r0 0 0 scl si cs 11 s0 0 0 d5 d4 d3 d2 d1 d0 don? care 0101110a0 i3 i2 i1 i0 0 0 0 sck si i n c 1 i n c 2 i n c n d e c 1 d e c n 0 cs sck si v w inc/dec cmd issued t wrid voltage out
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 9 of 21 www.xicor.com table 3. instruction set instruction instruction set operation i 3 i 2 i 1 i 0 r 1 r 0 read wiper counter register 1 0 0 1 0 0 0 0 read the contents of the wiper counter register write wiper counter register 1 0 1 0 0 0 0 0 write new value to the wiper counter register read data register 1 0 1 1 1/0 1/0 0 0 read the contents of the data register pointed to by r 1 ? 0 write data register 1 1 0 0 1/0 1/0 0 0 write new value to the data register pointed to by r 1 ? 0 xfr data register to wiper counter register 1 1 0 1 1/0 1/0 0 0 transfer the contents of the data register pointed to by r 1 ? 0 to the wiper counter register xfr wiper counter register to data register 1 1 1 0 1/0 1/0 0 0 transfer the contents of the wiper counter register to the data register pointed to by r 1 ? 0 increment/decrement wiper counter register 00100 0 0 0 enable increment/decrement of the wiper counter register read status (wip bit) 0 1 0 1 0 0 0 1 read the status of the internal write cycle, by checking the wip bit.
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 10 of 21 www.xicor.com instruction format notes: (1) ?0? stands for the device addresses sent by the master. (2) wpx refers to wiper position data in the wiper counter register ?? stands for the increment operation, si held high during active sck phase (high). (3) ?? stands for the decrement operation, si held low during active sck phase (high). read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) read the contents of the register pointed to by r1-r0. write data register (dr) write a new value to the register pointed to by r1-r0. transfer data register (dr) to wiper counter register (wcr) transfer the contents of the register pointed to by r1-r0 to the wcr. cs falling edge device type identifier device addresses instruction opcode wiper position (sent by x9421 on so) cs rising edge 0101110 a 0 1001000000 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode data byte (sent by host on si) cs rising edge 0101110 a 0 1010000000 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode register addresses data byte (sent by x9421 on so) cs rising edge 0101110 a 0 1011 r 1 r 0 0000 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode register addresses data byte (sent by host on si) cs rising edge high-voltage write cycle 0101110 a 0 1100 r 1 r 0 0000 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode register addresses cs rising edge 0101110 a 0 1101 r 1 r 0 00
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 11 of 21 www.xicor.com transfer wiper counter register (wcr) to data register (dr) increment/decrement wiper counter register (wcr) read status cs falling edge device type identifier device addresses instruction opcode register addresses cs rising edge high-voltage write cycle 0101110 a 0 1110 r 1 r 0 00 cs falling edge device type identifier device addresses instruction opcode increment/decrement (sent by master on sda) cs rising edge 0101110 a 0 00100000i/di/d ....i/di/d cs falling edge device type identifier device addresses instruction opcode data byte (sent by x9421 on so) cs rising edge 0101110 a 0 010100010000000 w i p
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 12 of 21 www.xicor.com absolute maximum ratings temperature under bias . . . . . . . . . . . . ?5 c to +135 c storage temperature . . . . . . . . . . . . . . ?5 c to +150 c voltage on sck any address input with respect to v ss . . . . . . . . . . . . . . . . . ?v to +7v ? v = | (v h ?v l ) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v lead temperature (soldering, 10 seconds) . . . . . . 300 c i w (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . ?ma any v h /r h , v l /r l , v w /r w . . . . . . . . . . . . v ss to v cc comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions temp min. max. commercial 0? +70? industrial ?0? +85? device supply voltage (v cc ) limits x9421 5v 10% x9421-2.7 2.7v to 5.5v analog characteristics (over recommended operating conditions unless otherwise stated.) notes: (1) absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position whe n used as a potentiometer. (2) relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. (3) mi = rtot/63 or (v h ? l )/63, single pot (4) typical = individual array resolution. symbol parameter limits test conditions min. typ. max. units end to end resistance tolerance ?0 % power rating 50 mw 25?, each pot i w wiper current ? ma r w wiper resistance 150 250 ? wiper current = 1ma, v cc = 5v 400 1000 ? wiper current = 1ma, v cc = 3v v term voltage on any v h /r h , v l /r l , v w /r w v ss v cc v v ss = 0v noise -120 dbv ref: 1khz resolution (4) 1.6 % see note 5 absolute linearity (1) ? mi (3) v w(n)(actual) ?v w(n)(expected) relative linearity (2) ?.2 mi (3) v w(n + 1) ?[v w(n) + mi ] temperature coefficient of r total 300 ppm/? see note 5 ratiometric temperature coefficient 20 ppm/? see note 5 c h /c l /c w potentiometer capacitances 10/10/25 pf see circuit #3 i al rh, ri, rw leakage current 0.1 10 ? vin = vss to vcc. device is in stand-by mode.
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 13 of 21 www.xicor.com d.c. operating characteristics (over the recommended operating conditions unless otherwise speci?d.) endurance and data retention capacitance power-up timing power up requirements (power up sequencing can affect correct recall of the wiper registers) the preferred power-on sequence is as follows: first v cc and then the potentiometer pins, r h , r l , and r w . voltage should not be applied to the potentiometer pins before v cc is applied. the v cc ramp rate speci?ation should be met, and any glitches or slope changes in the v cc line should be held to <100mv if possible. also, v cc should not reverse polarity by more than 0.5v. recall of wiper position will not be complete until v cc reaches its ?al value. notes: (5) this parameter is periodically sampled and not 100% tested. a.c. test conditions symbol parameter limits test conditions min. typ. max. units i cc1 v cc supply current (active) 400 ? f sck = 2mhz, so = open, other inputs = v ss i cc2 v cc supply current (non-volatile write) 1maf sck = 2mhz, so = open, other inputs = v ss i sb v cc current (standby) 1 a sck = si = v ss , addr. = v ss i li input leakage current 10 av in = v ss to v cc i lo output leakage current 10 av out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 0.5 v v il input low voltage ?.5 v cc x 0.1 v v ol output low voltage 0.4 v i ol = 3ma parameter min. units minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test max. units test conditions c out (5) output capacitance (so) 8 pf v out = 0v c in (5) input capacitance (a0, si, and sck) 6 pf v in = 0v symbol parameter max. max. units t r v cc (5) v cc power up ramp 0.2 50 v/msec i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 14 of 21 www.xicor.com ac timing symbol parameter min. max. units f sck ssi/spi clock frequency 2.0 mhz t cyc ssi/spi clock cycle time 500 ns t wh ssi/spi clock high time 200 ns t wl ssi/spi clock low time 200 ns t lead lead time 250 ns t lag lag time 250 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 50 ns t ri si, sck, hold and cs input rise time 2 s t fi si, sck, hold and cs input fall time 2 s t dis so output disable time 0 500 ns t v so output valid time 100 ns t ho so output hold time 0 ns t ro so output rise time 50 ns t fo so output fall time 50 ns t hold hold time 400 ns t hsu hold setup time 100 ns t hh hold hold time 100 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs 20 ns t cs cs deselect time 2 s t wpasu wp , a0 and a1 setup time 0 ns t wpah wp , a0 and a1 hold time 0 ns equivalent a.c. load circuit circuit #3 spice macro model 5v 1533 ? 100pf sda output 2.7v 100pf 10pf r h r total c h 25pf c w c l 10pf r w r l
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 15 of 21 www.xicor.com high-voltage write cycle timing xdcp timing symbol table symbol parameter typ. max. units t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. max. units t wrpo wiper response time after the third (last) power supply is stable 10 ? t wrl wiper response time after instruction issued (all load instructions) 10 ? t wrid wiper response time from an active scl/sck edge (increment/decrement instruction) 450 ns waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 16 of 21 www.xicor.com timing diagrams input timing output timing hold timing ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck so si addr msb lsb t dis t ho t v ... ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 17 of 21 www.xicor.com xdcp timing (for all load instructions) xdcp timing (for increment/decrement instruction) write protect and device address pins timing ... cs sck si msb lsb v w t wrl ... so high impedance ... cs sck so si addr t wrid high impedance v w ... inc/dec inc/dec ... cs wp a0 a1 t wpasu t wpah (any instruction)
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 18 of 21 www.xicor.com applications information electronic potentiometers provide three powerful application advantages: (1) the variability and reliability of a solid- state potentiometer, (2) the ?xibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. basic configurations of electronic potentiometers basic circuits v r v w v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current v h v l noninverting amplifier voltage regulator offset voltage adjustment comparator with hysterisis + v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + v s v o r 2 r 1 v ul = {r 1 /cr 1 +r 2 } v o (max) v ll = {r 1 /cr 1 +r 2 } v o (min) 100k ? 10k ? 10k ? 10k ? -12v +12v tl072 + v s v o r 2 r 1 } } +5v ?v lm308a cascading techniques buffered reference voltage + +5v r 1 +v ?v v w v w v out = v w op-07 v w v w +v +v +v x (a) (b)
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 19 of 21 www.xicor.com packaging information 16-lead plastic soic (300 mil body) package type s note: all dimensions in inches (in parentheses in millimeters) 0.014 (0.35) 0.020 (0.51) pin 1 pin 1 index 0.050 (1.27) 0.403 (10.2 ) 0.413 ( 10.5) (4x) 7 0.420" 0.050" typical 0.030" typical 16 places footprint 0.010 (0.25) 0.020 (0.50) 0.0075 (0.19) 0.010 (0.25) 0 C 8 x 45 0.050" typical 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) 0.015 (0.40) 0.050 (1.27)
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 20 of 21 www.xicor.com packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tssop, package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0?- 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
x9421 rev 1.1.6 8/1/02 characteristics subject to change without notice. 21 of 21 www.xicor.com limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2000 patents pending ordering information device v cc limits blank = 5v ?0% ?.7 = 2.7 to 5.5v temperature range blank = commercial = 0? to +70? i = industrial = ?0? to +85? package s = 16-lead soic v = 14-lead tssop potentiometer organization w =10k ? y =2.5k ? x9421 p t v y

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